The present invention relates to the field of integrated circuits, and, more particularly, to semiconductor non-volatile memory devices including complementary metal oxide semiconductor (CMOS) technology and related fabrication processes.
Non-volatile memories store charge on a floating gate, i.e., a gate not connected outside the device. The mode of injection or erasure of this charge depends on the type of memory in question. The control potential on the floating gate is induced by a capacitively coupled control gate. The charge may be injected or erased many times without appreciably damaging the structure. When the charge is stored on the floating gate, it can remain there a very long time (apart from leakage currents) without being impaired. This storage is said to be xe2x80x9cnon-volatile.xe2x80x9d
Among the non-volatile memories, mention is made here of erasable and programmable read-only memories (EPROMs) and electrically erasable and programmable read-only memories (EEPROMs), as well as the so-called xe2x80x9cFlash EPROMsxe2x80x9d or xe2x80x9cFlash EEPROMsxe2x80x9d. Depending upon the type of non-volatile memory, charge is introduced into the floating gate either by the injection of hot carriers from the channel of the transistor or by forcing conduction through the oxide. This modifies the threshold voltage of the transistor. To discharge the floating gate (i.e., to erase the contents of the memory), either illumination by ultraviolet radiation is used (e.g., in an EPROM memory), thereby making the oxide conducting, or a discharge by a tunnel effect is used.
A non-volatile point memory MMA according to the prior art is illustrated in FIG. 1. The memory device MMA has two polysilicon levels PL1 and PL2 above the upper surface UPS of the substrate SB. These levels PL1, PL2 form the floating gate FG and the control gate CG, respectively, of the memory device. The floating gate FG is electrically isolated from the source region S, the drain region D, and the channel region CR by a first oxide layer OX1. The floating gate and the control gate are mutually electrically isolated by a second oxide layer OX2. Lateral isolating regions or spacers SPA complete the electrical isolation of the two gates, especially that of the floating gate FG. The use of two levels of polysilicon has drawbacks, especially from the standpoint of integrating a point memory therewith in a more complex structure using CMOS technology.
An object of the invention is to provide a non-volatile memory device using only a single polysilicon level above the surface of the substrate.
According to the invention, a semiconductor non-volatile memory device includes a silicon-based semiconductor substrate including source and drain regions, a control gate, and a floating gate. The floating gate extends between the source and drain regions formed in the substrate, and the control gate lies above the floating gate. In other words, whereas in the prior art the floating gate is above the source and drain regions, in this case it is xe2x80x9cburiedxe2x80x9d in the substrate. Thus, only a single polysilicon level above the upper surface of the substrate is required to form the control gate.
More specifically, the substrate has a lower part or portion lying beneath the source and drain regions and a channel region lying above the lower part of the substrate between the source and drain regions. The floating gate may be formed from a semiconductor region overdoped with respect to the channel region. The semiconductor region lies above the channel region and is isolated therefrom and from the source and drain regions by an insulating layer.
The non-volatile memory device may also include an additional insulating layer between the channel region and the lower part of the substrate. Thus, the channel of the MOS transistor is bounded by two isolating regions, thereby making it possible to obtain narrow and confined channels. This gives the channels great robustness, as opposed to the drawbacks associated with the effects of short channels.
Apart from the fact that the floating gate is buried in the initial surface of the silicon wafer, it is advantageously a single-crystal silicon gate. The floating gate may be longer than the control gate in the channel direction. Further, it may be confined, in a perpendicular direction, to the width of the active region. This is not the case with the control gate.
A method aspect of the invention is for fabricating a semiconductor non-volatile memory device and includes forming a first layer of a material on an initial silicon substrate. The first layer is surrounded by an isolating peripheral region and may be removed selectively with respect to the silicon. The first layer may comprise a silicon-germanium alloy, for example. Further, a silicon second layer is formed on the first layer and overdoped (e.g., in situ or by implantation) with respect to the initial substrate, and a gate oxide layer is formed on the second layer. A control gate is formed on the gate oxide layer and contacts, at opposing ends thereof, the isolating peripheral region. Additionally, the gate oxide layer, the second layer, the first layer, and an upper part of the initial substrate are etched along two opposed sidewalls of the gate to form cavities. The first layer is selectively etched to form a tunnel between the second layer and the initial substrate, and an insulating layer is formed on the walls of the second layer and in at least part of the tunnel. Further, the cavities may be filled with silicon, and the source and drain regions may be formed in the filled cavities, on each side of the second layer, to form a floating gate.
More specifically, forming the insulating layer may include coating the walls of the tunnel with the insulating layer, where the inside of the tunnel is empty. Alternatively, forming the insulating layer may include completely filling the tunnel with the insulating layer. Either way, forming the insulating layer may also include forming the insulating layer in the bottom of the cavities. In this case, that part of the insulating layer formed in the bottom of the cavities is removed before filling the cavities with silicon. Further, that part of the insulating layer formed in the bottom of the cavities may be removed by anisotropic etching or by chemical etching in a wet bath.
It is also advantageous, before oxidizing the tunnel, to implant selected ions into the bottom of the cavities (e.g., nitrogen ions) to retard the oxidation of the silicon. Thus, a thinner insulating layer is obtained in the bottom of the cavities after the insulating step than inside the tunnel. In this way, it will be possible after the insulating step to maintain an insulating layer on the lower wall of the tunnel. This makes it possible to obtain a point memory whose channel is confined by two oxide layers. Additionally, the silicon may be grown by selective epitaxy during the cavity-filling step. The silicon may optionally fill the inside of the tunnel (if the tunnel has not otherwise been completely filled with oxide).